S4403

• Generates six clock outputs from 20 MHz to 80 MHz (the S4403 generates ten outputs and HFOUT generates 10MHz to 40MHz)
• 21 selectable phase/frequency relationships for the clock outputs
• Compensates for clock skew by allowing output delay adjustment down to 3.125 ns increments
• TTL outputs have less than 400 ps maximum skew
• Lock Detect output indicates loop status
• Internal PLL with VCO operating at 160 to 320 MHz
• Test Enable input allows V_CO bypass for openloop operation in board test
• Maximum 1.0 ns of phase error (750 ps from part to part)
• Proven 1.0 micron BiCMOS technology
• Single +5V power supply operation
• 28/44 PLCC packages

The S4402/S4403 BiCMOS clock generators allow the user to generate multiphase TTL clocks in the 1080 MHz range with less than 400 ps of skew. Use of a single off-chip filter allows an entire 160320 MHz phase-locked loop (PLL) to be implemented onchip.

Divide-by-two and times-two outputs (S4403)allow the ability to generate output clocks at half, equal to, or twice the reference clock input frequency. By using the programmable divider and phase selector, the user can select from up to 21 different output relationships.

The outputs of S4403 can be phase-adjusted in increments as small as 3.125 ns to tailor the clocks to exact system requirements.

Implemented in AMCC's proven 1.0 micron BiCMOS technology, the S4402 generates six TTL outputs, while the S4403 provides those six plus four duplicates (FOUT0AFOUT3A) for a total of ten. Output enables are provided for the various banks, allowing clock control for board and system tests.