S4405

The S4405 BiCMOS clock generators allow the user to generate multiphase TTL clocks in the 1080 MHz range with less than 400 ps of skew. Use of a simple off-chip filter allows an entire 160320 MHz phaselocked loop (PLL) to be implemented on-chip. Divideby- two and times-two outputs allow the ability to generate output clocks at half, equal to, or twice the reference clock input frequency. The reference is selectable to be either TTL or PECL. By using the programmable divider and phase selector, the user can select from up to 21 different output relationships.

The outputs of S4405 can be phase-adjusted in increments as small as 3.125 ns to tailor the clocks to exact system requirements.

Implemented in AMCC's proven 1.0 micron BiCMOS technology, the S4405 generates six TTL outputs and one differential PECL output. Output enables are provided for the various TTL banks, allowing clock control for board and system tests.