SAA3323

` Operating supply voltage: 2.7 to 3.6 V
` Low power dissipation: 84 mW (typ)
` Single chip digital equalizer, tape formatting and error correction
` 8-bit flash analog-to-digital converter (ADC) for low symbol error rate
` Two switchable Infinite Impulse-Response (IIR) filter sections
` 10-tap Finite Impulse-Response (FIR) filter per main data channel, with 8 bit coefficients, identical for all main channels
` 10-tap FIR filter for the AUX channel
` Analog and digital eye outputs
` Interrupt line triggered by internal auxiliary envelope processing e.g. label, counter, and others
` Robust programmable digital PLL clock extraction unit
` Low power SLEEP mode
` Slew rate limited Electromagnetic Compatibility (EMC) friendly output
` Digital Compact Cassette (DCC) optimized error correction
` Programmable symbol synchronization strategy for tape input data
` Microcontroller control of capstan servo possible during playback and recording
` Frequency and phase regulation of capstan servo
during playback
` Choice of Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) types for system Random Access Memory (RAM)
` Scratch pad RAM for microcontroller in system RAM
` Integrated interface for Precision Adaptive Sub-band Coding (PASC) data bus
` Three wire microcontroller 'L3' interface
` Protection against invalid auxiliary data
` Seamless joins between recordings.

The SAA3323 performs the drive processor function in the DCC system. This function is built up of digital equalizer, error correction and tape formatting functions. The digital equalizer is intended for use with DCC read amplifiers TDA1318 or TDA1380. The tape formatting and error correction circuit is intended for use with PASC ICs SAA2003 and SAA2013, and write amplifiers TDA1319 or TDA1381.