SAA4981

The integrated 16 : 9 compressor is an IC which compresses the active part of a video line by a factor of 4/3 from, for example, 52 ms to 39 ms. This is necessary to display 4:3 video software on a 16 : 9 tube in the correct proportion. The capacitively coupled video inputs are Y, (B-Y) and (R-Y).

The synchronisation input HREF is a line frequency reference signal. The bandwidth of the IC is up to 5 MHz and the signal delay is realized with SC Line Memories (Switched Capacitors Line Memories). The output of the 16 : 9 compressor also has the format Y, (B-Y) and (R-Y) and provides the following two possibilities:
1. Bypass function (the input signal is not compressed)
2. Compressed video by a factor of 4/3 with three different fixed screen positions (left, centre and right). The luminance and chrominance of the side panels are determined by the external signals YSIDE, BYSIDE and RYSIDE.

The horizontal compression is a time discrete and amplitude continuous signal processing. This provides pre and post filters which are realized on-chip. The internal clock generation is achieved with a 54 MHz horizontal PLL which is synchronized to the positive edge of the HREF signal. The function of the IC is controlled by the three control signals CTRL1, CTRL2 and CTRL3.