Features: · Horizontal sample rate conversion in both zoom and compress direction, with a sample rate conversion factor between 0.5 and 2 (in 384 steps)· Dynamic sample rate conversion for panorama mode display e.g. 4 : 3 material on a 16 : 9 display· Dynamic sample rate conversion for amaronap mo...
SAA4995WP: Features: · Horizontal sample rate conversion in both zoom and compress direction, with a sample rate conversion factor between 0.5 and 2 (in 384 steps)· Dynamic sample rate conversion for panorama ...
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· Horizontal sample rate conversion in both zoom and compress direction, with a sample rate conversion factor between 0.5 and 2 (in 384 steps)
· Dynamic sample rate conversion for panorama mode display e.g. 4 : 3 material on a 16 : 9 display
· Dynamic sample rate conversion for amaronap mode display of e.g. 16 : 9 material on a 4 : 3 display
· Operates with 1fh and 2fh
· Programmable via microcontroller SNERT (Synchronous No parity Eight bit Receive Transmit) bus.

| SYMBOL | PARAMETER | CONDITIONS | MIN. | MAX. | UNIT |
| VDD | supply voltage | -0.5 | +6.5 | V | |
| Vi, Vo | input and output voltages | -0.5 | VDD + 0.5 | V | |
| Io/out | output current per output pin | - | 20 | mA | |
| P/out | power dissipation per output pin | - | 100 | mW | |
| Tstg | storage temperature | -55 | +140 | °C | |
| Tamb | operating ambient temperature | -40 | +85 | °C | |
| VESD | electrostatic handling for all pins | note 1 | - | ±2000 | V |
| note 2 | - | ±300 | V |
The PAN-IC is an add-on IC to be used, for example, between analog-to-digital conversion and a serial (field) memory. The SAA4995WP performs the following tasks:
· Linear horizontal sample rate conversion in both zoom and compress direction, with a sample rate conversion factor between 0.5 and 2
· Dynamic sample rate conversion for panorama mode display of e.g. 4 : 3 material on a 16 : 9 display
· Dynamic sample rate conversion for amaronap mode display of e.g. 16 : 9 material on a 4 : 3 display.
The PAN-IC SAA4995WP has the ability to increase the data rate from the ADC to a maximum of twice the data rate at the output. To achieve this a clock rate at twice the normal output clock rate is needed to write data to the memory.
All actions to generate a lower data rate, produces disable cycles in Write Enable (WE).