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Part Number: SAA7110

 

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Description: The one chip front-end SAA7110; SAA7110A is a digital multistandard colour decoder (OCF1) on the basis...


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SAA7110 General Description


The one chip front-end SAA7110; SAA7110A is a digital multistandard colour decoder (OCF1) on the basis of the DIG-TV2 system with two integrated Analog-to-Digital Converters (ADCs), a Clock Generation Circuit (CGC) and Brightness Contrast Saturation (BCS) control.

The CMOS circuit SAA7110; SAA7110A, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding. It operates square-pixel frequencies to achieve correct aspect ratio. Monitor controls are provided to ensure best display. The circuit is I2C-bus controlled.

SAA7110 Maximum Ratings

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDDA analog supply voltage   -0.5 +7.0 V
VDDD digital supply voltage   -0.5 +7.0 V
VI(A) analog input voltage   -0.5 +7.0 V
VI(D) digital input voltage   -0.5 +7.0 V
Vdiff voltage difference between VSSAall and VSSall   - 100 mV
Tstg storage temperature   -65 +150 °C
Tamb operating ambient temperature   0 70 °C
Tamb(bias) operating ambient temperature under bias   -10 +80 °C
Ptot total power dissipation VDDA = VDDD = 7 V; note 1 - 2.5 W
Vesd electrostatic discharge all pins note 2 -2000 +2000 V

Note
1. Compare with typical total power consumption in Chapter "Characteristics".
2. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

SAA7110 Features

` Six analog inputs (6 * CVBS or 3 * Y/C or combinations)
` Three analog processing channels
` Three built-in analog anti-aliasing filters
` Analog signal adding of two channels
` Two 8-bit video CMOS analog-to-digital converters
` Fully programmable static gain for the main channels or automatic gain control for the selected CVBS/Y channel
` Selectable white peak control signal
` Luminance and chrominance signal processing for PAL B/G, NTSC M and SECAM
` Full range HUE control
` Automatic detection of 50/60 Hz field frequency, and automatic switching between standards PAL and NTSC, SECAM forceable
` Horizontal and vertical sync detection for all standards
` Cross-colour reduction by chrominance comb filtering for NTSC or special cross-colour cancellation for SECAM
` UV signal delay lines for PAL to correct chrominance phase errors
` The YUV-bus supports a data rate of:
   780 * fh = 12.2727 MHz for 60 Hz (NTSC)
   944 * fh = 14.75 MHz for 50 Hz (PAL/SECAM)
` Square pixel format with 768/640 active samples per line on the YUV-bus
` CCIR 601 level compatible
` 4 : 2 : 2 and 4 : 1 : 1 YUV output formats in 8-bit resolution
` User programmable luminance peaking for aperture correction
` Compatible with memory-based features (line-locked clock, square pixel)
` Requires only one crystal (26.8 MHz) for all standards
` Real time status information output (RTCO)
` Brightness Contrast Saturation (BCS) control for the YUV-bus
` Negation of picture possible
` One user programmable general purpose switch on an output pin
` Switchable between on-chip Clock Generation Circuit (CGC) and external CGC (SAA7197)
` Power-on control
` I2C-bus controlled.

SAA7110 Typical Application

· Desktop video
· Multimedia
· Digital television
· Image processing
· Video phone
· Video picture grabbing.

SAA7110 Connection Diagram

SAA7110  Connection Diagram

SAA7110 datasheet

SAA7110
PDF/DataSheet Download

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