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Part Number: SAA7111

 

MFG: PHI

 

D/C: 07+

Description: The Video Input Processor (VIP) is a combination of a two-channel analog preprocessing circuit includi...


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SAA7111 General Description


The Video Input Processor (VIP) is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, NTSC M and NTSC N), a brightness/contrast/saturation control circuit and a colour space matrix (see Fig.1).

The CMOS circuit SAA7111, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL and NTSC signals into CCIR-601 compatible colour component values. The SAA7111 accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I2C-bus controlled.

SAA7111 Maximum Ratings

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDDD digital supply voltage   -0.5 +6.5 V
VDDA analog supply voltage   -0.5 +6.5 V
Vdiff voltage difference between VSSAall and

VSSall
  - 100 mV
Tstg storage temperature   -65 +150 °C
Tamb operating ambient temperature   0 70 °C
Tamb(bias) operating ambient temperature under bias   -10 +80 °C
VESD electrostatic discharge all pins note 1 -2000 +2000 V

Note
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor.

SAA7111 Features

` Four analog inputs, internal analog source selectors, e.g. 4 * CVBS or 2 * Y/C or (1 * Y/C and 2 * CVBS)
` Two analog preprocessing channels
` Fully programmable static gain for the main channels or automatic gain control for the selected CVBS or Y/C channel
` Switchable white peak control
` Two built-in analog anti-aliasing filters
` Two 8-bit video CMOS analog-to-digital converters (ADCs)
` On-chip clock generator
` Line-locked system clock frequencies
` Digital PLL for H-sync processing and clock generation
` Requires only one crystal (24.576 MHz) for all standards
` Horizontal and vertical sync detection
` Automatic detection of 50/60 Hz field frequency and automatic switching between standards PAL and NTSC
` Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N and NTSC 4.43
` User programmable luminance peaking or aperture correction
` Cross-colour reduction for NTSC by chrominance comb filtering
` PAL delay line for correcting PAL phase errors
` Real time status information output (RTCO)
` Brightness Contrast Saturation (BCS) control on-chip
` The YUV (CCIR-601) bus supports a data rate of:
   864 * fH = 13.5 MHz for 625 line sources
   858 * fH = 13.5 MHz for 525 line sources.
` Data output streams for 16, 12 or 8-bit width with the following formats:
   411 YUV (12-bit)
   422 YUV (16-bit)
   422 YUV [CCIR-656] (8-bit)
   565 RGB (16-bit) with dither
   888 RGB (24-bit) with special application.
` 720 active samples per line on the YUV bus
` One user programmable general purpose switch on an output pin
` Built in line-21 text slicer
` Power-on control
` Two switchable outputs for the digitized CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0) via the I2C-bus
` Chip enable function (reset for the clock generator)
` Compatible with memory-based features (line-locked clock)
` Boundary scan test circuit complies with the IEEE Std. 1149.1 - 1990 (ID-Code = 0 7111 02 B)
` I2C-bus controlled (full read-back ability by an external controller).

SAA7111 Typical Application

· Desktop video
· Multimedia
· Digital television
· Image processing
· Video phone.

SAA7111 Connection Diagram

SAA7111  Connection Diagram

SAA7111 datasheet

SAA7111
PDF/DataSheet Download

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