SAA7126H

` Monolithic CMOS 3.3 V device, 5 V I2C-bus optionally
` Digital PAL/NTSC encoder
` System pixel frequency 13.5 MHz
` 54 MHz double-speed multiplexed D1 interface capable of splitting data into two separate channels (encoded and baseband)
` Four Digital-to-Analog Converters (DACs) for CVBS (CSYNC, VBS), RED (Cr, C), GREEN (Y, VBS) and BLUE (Cb, CVBS) two times oversampled (signals in parenthesis are optionally). RED (Cr), GREEN (Y) and BLUE (Cb) signal outputs with 9-bit resolution, whereas all other signal outputs have 10-bit resolution; CSYNC is an advanced composite sync on the CVBS output for RGB display centring.
` Real-time control of subcarrier
` Cross-colour reduction filter
` Closed captioning encoding and World Standard Teletext (WST) and North-American Broadcast Text System (NABTS) teletext encoding including sequencer and filter
` Copy Generation Management System (CGMS) encoding (CGMS described by standard CPR-1204 of EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via the I2C-bus
` Fast I2C-bus control port (400 kHz)
` Line 23 Wide Screen Signalling (WSS) encoding
` Video Programming System (VPS) data encoding in line 16 (CCIR line count)
` Encoder can be master or slave
` Programmable horizontal and vertical input synchronization phase
` Programmable horizontal sync output phase
` Internal Colour Bar Generator (CBG)
` Macrovision Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; 'handsfree' Macrovision pulse support through on-chip timer for pulse amplitude modulation; this applies to SAA7126H only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information.
` Controlled rise/fall times of output syncs and blanking
` On-chip crystal oscillator (3rd-harmonic or fundamental crystal)
` Down mode (low output voltage) or power-save mode of DACs
` QFP44 package.

The SAA7126H; SAA7127H encodes digital Cb-Y-Cr video data to an NTSC or PAL CVBS or S-video signal. Simultaneously, RGB or bypassed but interpolated Cb-Y-Cr signals are available via three additional Digital-to-Analog Converters (DACs). The SAA7126H; SAA7127H at a 54 MHz multiplexed digital D1 input port accepts two CCIR compatible Cb-Y-Cr data streams with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data with overlay and MPEG decoded data without overlay, whereas one data stream is latched at the rising, the other one at the falling clock edge.

SAA7126H; SAA7127H include a sync/clock generator and on-chip DACs.