Features: ` Input data fully compliant with the Transport Stream (TS) definition of the MPEG-2 systems specification
` Input data signals; [Forward Error Correction (FEC) Interface]
modem data input bus (8-bit wide)
valid input data indicator
erroneous packet indicator
first packet byte indicator
byte strobe signal (for asynchronous mode only).
The interface can be programmed to one of two modes:
Asynchronous mode; byte strobe input signal (MBCLK) < 9 MHz, for connection to a modem (FEC)
Synchronous mode; MBCLK is not used. Data is delivered to the descrambler synchronized with the chip clock (DCLK) [9 MHz (typ.) with a 33% duty cycle].
` No external memory
` Effective bit rate; fbit 72 MHz
` Control interface; 8-bit multiplexed data/address, memory mapped I/O (90CE201 microcontroller parallel bus compatible), in combination with a microcontroller interrupt signal (IRQ)
` Output ports are identical to the input data interface (demultiplexer interface)
except for the packet error indicator (MB/MB), as the descrambler translates an active MB signal to the'transport_error_indicator' bit in the transport stream
except for the byte strobe input signal (MBCLK), as data is delivered to the demultiplexer, synchronized with the descrambler chip clock which is generated by the demultiplexer
` Descrambler, based on the super descrambler mechanism algorithm with stream decipher and block decipher. The descrambler is initialized with a 64-bit Control Word (CW) at the beginning of a transport stream packet payload of a selected Packet Identification (PID). The descrambler operates on transport stream packet or Packetized Elementary Stream (PES) packet payloads
` Microcontroller support; only for control, no specific descrambling tasks are performed by the microcontroller. However, parsing and processing of conditional access information (such as EMM and ECM data) is left to the system microcontroller
` Boundary scan test port for boundary scan.
Pinout
Specifications
| SYMBOL |
PARAMETER |
MIN. |
MAX. |
UNIT |
| VDDD(pads) |
digital supply voltage for pads (+5 V) |
-0.5 |
+6.5 |
V |
| VDDD(core) |
digital supply voltage for core (+3.3 V) |
-0.5 |
+5.0 |
V |
| VI |
DC input voltage |
-0.5 |
VDDD + 0.5 |
V |
| VO |
DC output voltage; |
-0.5 |
VDDD + 0.5 |
V |
| IDDD, ISSD |
DC current; VDD or VSS |
- |
52 |
mA |
| Ii(max) |
maximum input current |
-10 |
+10 |
mA |
| Io(max) |
maximum output current |
-20 |
+20 |
mA |
| Ptot |
total power dissipation |
- |
250 |
mW |
| Tstg |
storage temperature |
-65 |
+150 |
°C |
| Tamb |
operating ambient temperature |
0 |
70 |
°C |
DescriptionThe SAA7206H (DVB compliant) is designed for use in MPEG-2 based digital TV receivers, incorporating conditional access filters. Such receivers of SAA7206H are to be implemented in, for instance, a digital video broadcasting top set box, or an integrated digital TV receiver. An example of a demultiplexer/descrambler system configuration, containing a channel decoder module, a demultiplexer, a system controller and a conditional access system is shown in Fig.3. The main function of the SAA7206H descrambler is to descramble the payloads of MPEG-2 TS packets or PES packets. In addition, the descrambler retrieves Conditional Access (CA) data [such as Entitlement Management Messages (EMM) and Entitlement Control Messages (ECM) etc.] from the stream and passes it to the system microcontroller for processing.
SAA7206H Data Sheet
