SAA7240

1.1 General
` Conditional access descrambling Digital Video Broadcasting (DVB) compliant, MULTI2 compliant and ICAMâ (1) compliant
` Targeted to BSkyB 3.00 and Canal+ basic box 3.02 and web box 1.01 applications
` Stream demultiplexing: Transport Stream (TS), Packetized Elementary Stream (PES), Program Stream (PS) and Proprietary data streams
` Internal 32-bit MIPS RISC-based CPU, supporting MIPS16 instruction set and running at 81 MHz
` Low-power Sleep modes supported across the chip
` Support for external co-processor
` 0.25 mm technology
` Power supply of 2.5 V for the core and 3.3 V for the peripherals, to be TTL level compatible
` Comprehensive driver software and development tool support
` Package: SQFP208.
1.2 External interfaces
The SAA7240 supports the following external interfaces:
` Versatile transport stream input/output at 13.5 Mbytes/s configurable in parallel or serial mode. Interfaces to IEEE 1394 devices (such as Philips PDI 1394 chip-set) in full-duplex mode and to external descramblers through a Common Interface (CI) device. The following interfaces are supported:
3 parallel TS input/output ports
2 parallel TS input/output ports and 3 serial TS ports
1 parallel TS input/output port and 5 serial TS ports
6 serial TS input/output ports.
` A microcontroller extension bus, supporting:
16-bit and 32-bit data buses
Up to 64 Mbytes addressing range
Synchronous Dynamic RAM (SDRAM) interface
Dynamic RAM interface
Read Only Memory (ROM) interface
Flash memory interface
Interface to various peripherals
Synchronous interface to communicate with the integrated MPEG Audio Video Graphics Decoder (AVGD) SAA7215 at 40.5 MHz
Large endian and small endian byte addressing
A multi-master mode (master and slave modes).
` 2-channel Direct Memory Access (DMA) for fast block move to/from any memory location
` Up to 12 chip selects available, some can be configured as general purpose ports
` An IEEE 1284 interface (Centronics) with DMA engine supporting master and slave modes. Usable as a general purpose port
` Two UART (RS232) data ports with DMA capabilities (at 187.5 kbit/s), including hardware flow control signals RXD, TXD, RTS and CTS for modem support
` A Synchronous Serial Interface (SSI) to connect an off-chip modem analog front-end
` An elementary UART with DMA capabilities, dedicated to front panel devices for instance
` Two dedicated smart card reader interfaces (ISO 7816 compatible) with DMA capabilities. One interface is intended for the conditional access and is shared with the Integrated Conditional Access Module (ICAM) when ICAM is enabled; the second interface may be used for pay-per-view
` Two I2C-bus master/slave transceivers with DMA capabilities, supporting the standard (100 kbit/s) and fast (400 kbit/s) I2C-bus modes
` 32-bit general purpose port
` Eight interrupt inputs
` Parallel audio video interface to the MPEG AVGD decoder SAA7215
` One Pulse Width Modulated (PWM) output with 8-bit resolution
` An Extended JTAG (EJTAG) interface for board test support.
1.3 CPU-related features
The SAA7240 contains an embedded RISC CPU, which incorporates the following features:
` A 32-bit PR3930 core, running at 81 MHz
` Support for large and small byte addressing modes; is ready for Windowsâ (1)CE and pSOSâ (2) operating systems
` 8-kbyte 2-way set of associative instruction cache
` 4-kbyte 4-way set of associative data cache
` A programmable low-power mode, including wake-up on interrupt
` A Memory Management Unit (MMU) with 32 odd/even entries and variable page sizes
` Multiply/accumulate/divide unit with fast multiply/accumulate for 16-bit and 32-bit operands
` Two fully independent 24-bit timers and one 24-bit timer, including watchdog facilities
` A real-time clock unit (active in Sleep mode)
` Built-in software debug support unit as part of extended JTAG debug interface
` On-chip SRAM of 4 kbytes for storing code that needs fast execution.
1.4 MPEG-2 System Processor (MSP) features
` A flexible re-router to support many combinations of the transport stream input/output interfaces:
Connection to serial or parallel Common Interface IC
Connection to serial or parallel 1394 IC in full-duplex mode
Static dual front-end handling of channel decoders
A maximum frequency of up to 13.5 Mbytes/s in parallel mode and up to 81 Mbits/s in serial mode.
` A demultiplexer scheme, which is fully compliant with Canal+ and BSkyB specifications:
Hardware-based parsing of transport, program and proprietary software data streams. The maximum input rate is 13.5 Mbytes/s in parallel mode and 81 Mbits/s in serial mode
Up to 40, 13-bit Packet Identifier (PID) filters applied on the PID value. 32 PID filters can be dedicated to filter packets containing sections; four PID filters to filter transport packets header; four PID filters to parse audio, video, teletext and subtitle data
4 TS/PES packet header filters (filter condition of 3 bytes, including PID value for TS packet header and specific filter condition for PES packet header)
32 section filters based on a flexible number of filter conditions to retrieve PSI, SI, Private data and EPG, etc. Each section filter supports 48 filters conditions of 12 bytes; each filter condition can be negated or masked on a bit level
7 ECM/EMM filters stored in on-chip RAM for ICAM implementation (ECM/EMM packets are stored in on-chip RAM)
Flexible 40 channel DMA-based storage of the 32 section sub-streams and four TS/PES data sub-streams and 4 TS/PES packet headers in external memory
System time base management with a double counter mechanism for clock control and discontinuity handling
Two Presentation Time Stamp (PTS)/Decoding Time Stamp (DTS) timers
A General Purpose/High Speed (GP/HS) filter, which can serve as an alternative input from IEEE 1394 devices, for example. The IEEE 1394 GP/HS mode supports packet insertion and has an internal SRAM for storing two packets. It can also output either scrambled or descrambled TS to IEEE 1394 devices.
` A real time descrambler, supporting different descrambler algorithms and consisting of four modules:
A control word bank, containing 14 pairs (odd or even) of control words and a default control word
The DVB descrambler core, implementing the stream decipher and block decipher algorithms
The MULTI2 descrambler algorithm, implementing the CBC and OFB mode descrambling functions. In this mode, the maximum frequency is 9 Mbytes/s (72 Mbits/s)
The Integrated Conditional Access Module (ICAM), including an ISO 7816 compliant UART to interface the conditional access smart card.
1.5 Compatibility with other devices
The SAA7240 seamlessly interfaces to the integrated MPEG AVGD decoder SAA7215HS. It is also backward compatible with the other devices of the family. The following modes/combinations are supported:
` SAA7240 with SAA7215HS seamless
` Pinning compatibility with the SAA7219HS.

Notes
1. System designers should be aware that:
a) The IC junction temperature (Tj) is greatly influenced by the environment and the Printed-Circuit Board (PCB) layout thermal behaviour. Total allowable power Ptot in the customer application depends on its thermal characteristics; thermal resistance from junction to air; (Rth(j-a), refer to Chapter 8) and ambient temperature Tamb. Ptot(max) = (T_j(max) - Tamb)/Rth(j-a) = PINT + PI/O. PINT represents the internal device power (core and PLL). PI/O is the power dissipation in the input and output buffers. PINT depends on the user application and is limited by the maximum drive capability of the output buffers.
b) Table 3 gives some examples of theoretical maximum power dissipation supported by the package; the designer has to check that there is no IDDP maximum current violation.
2. This value represents the maximum current that the power track can carry without excessive voltage drop in the internal chip. This value does not reflect the maximum current consumption of the core, which is far below this value.
3. This theoretical maximum value which should never be exceeded is determined when all output buffers are driving heir specified maximum static drive current. In a standard application, this worst case never occurs because the output loads are mainly line capacitance and not resistive loads.

The SAA7240 is a transport MPEG-2 source decoder designed for application in set-top boxes in a Digital Video Broadcast (DVB) environment. It is targeted to BSkyB 3.00 and Canal+ basic box and web box applications. The device is part of a comprehensive source decoding kit that contains all the hardware and software required to receive and decode MPEG-2 transport streams, including descrambling and demultiplexing. In addition, it includes a PR3930 core, which is a 32-bit MIPS RISC-based CPU core supporting the MIPS16 instruction set (to reduce memory requirements) and several peripheral interfaces such as UARTs, I2C-bus units, an IEC 1883, and an IEEE 1284 (Centronics) interface. The SAA7240 is therefore capable of performing all controller tasks in digital television applications. Furthermore, the SAA7240 complies with DVB, ICAM and MULTI2 descrambler standards.

The SAA7240 receives transport streams through a versatile stream input interface capable of handling both byte-parallel and bit-serial streams, in various formats, supporting data streams up to and including 13.5 Mbytes/s in parallel mode and 81 Mbits/s in serial mode. The data stream of SAA7240 is first applied to an on-chip descrambler with a DVB descrambling algorithm, on the basis of 14 control word pairs stored in an on-chip RAM. Demultiplexing is subsequently applied to the data stream, to separate up to 40 individual data streams.

The demultiplexer section of SAA7240 includes clock recovery and timebase management. Program Specific Information (PSI), Service Information (SI), Conditional Access (CA) messages and private data are selected and stored in external memory, for subsequent off-line processing by the internal PR3930 CPU core. To support advanced board testing facilities, the SAA7240 includes Boundary Scan Test (BST) hardware, according to the JTAG standard. The SAA7240 features flexible low-power Sleep modes, which independently control the activity of each functional block and can sustain set-top box standby functionality, thus eliminating the need for a separate front-panel controller.

The SAA7240 requires a supply voltage of 3.3 V for the I/O pads and a supply voltage of 2.5 V for the core.