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SAA7385

Application1.1 General· Single chip digital solution for an 8 × speed CD-ROM controller chip· 10 Mbytes/s NCR53CF94 equivalent SCSI controller included· High-speed 80C32 microcontroller with 256 × 8 scratch-pad SRAM included· High performance CD-ROM interface logic· 128 pin QFP package.1.2 53CF94 ...

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SeekIC No. : 004484074 Detail

SAA7385: Application1.1 General· Single chip digital solution for an 8 × speed CD-ROM controller chip· 10 Mbytes/s NCR53CF94 equivalent SCSI controller included· High-speed 80C32 microcontroller with 256 × 8...

SAA7385 Data Sheet

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Part Number:
SAA7385
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Application

1.1 General

· Single chip digital solution for an 8 × speed CD-ROM controller chip
· 10 Mbytes/s NCR53CF94 equivalent SCSI controller included
· High-speed 80C32 microcontroller with 256 × 8 scratch-pad SRAM included
· High performance CD-ROM interface logic
· 128 pin QFP package.

1.2 53CF94 SCSI controller

· Separate clock input to allow operation up to the maximum 10 Mbytes/s
· Fast synchronous SCSI-2 compatible
· 24-bit transfer counter for single transfers up to 16 Mbytes
· High-speed 16-bit DMA interface to the buffer manager DRAM
· On-chip 48 mA SCSI drivers
· Software compatible with members of the 53C90 family
· Allows for SCAM support.

1.3 80C32 high-speed microcontroller

· 33.87 MHz full system speed operation
· Three timers/event counters
· Programmable full duplex serial channel
· Eight general purpose microcontroller I/O pins
· External program ROM.

1.4 Front-end interface logic

· Full 8 × speed hardware operation
· Block decoder
· Sector sequencer
· CRC checking of Mode 1 and Mode 2, Form 1 sectors
· 212 ms watch-dog timer
· Sub-code interface with synchronization
· C-flag interface for absolute time stamp.

1.5 Buffer controller

· Ten level arbitration logic
· Utilizes low cost 70 ns DRAMs
· Page mode DRAM access for high-speed error correction and SCSI data transfer
· Data organization by 3 kbyte frames
· 256 kbyte or 1 Mbyte DRAM supported.

1.6 Hardware third-level error correction

· Third-level correction provides superior performance in unfavourable conditions
· Full hardware error correction to reduce microcontroller overhead
· Corrections are automatically written to the DRAM frame buffer.

1.7 Additional product support

· All control registers mapped into 80C32 special function memory space
· Dedicated S2B interface UART
· Input clock synthesizer
· Red book audio pass through.


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER MIN. MAX. UNIT
VDD digital supply voltage -0.5 +7 V
Vi(max) maximum input voltage on any pin VSS - 0.5 VDD + 0.5 V
Vo output voltage on any output -0.5 +7 V
Tstg storage temperature -55 +150 °C



Description

The SAA7385 is a high integration ASIC that incorporates all of the digital electronics necessary to connect a CD
decoder to a SCSI host. An 80C32 microcontroller and a 53CF94 SCSI controller are embedded in the ASIC.

The following functions of SAA7385 are supported:

· Input clock doubler
· Block decoder
· CRC checking of Mode 1 and Mode 2, Form 1 sectors
· Red book audio pass through to SCSI
· Buffer manager
· Third-level error correction
· Sub-code and Q-channel support
· Dedicated S2B interface UART
· Embedded 80C32 microcontroller
· Embedded 53CF94 SCSI controller.

The SAA7385 uses a 33.8688 MHz clock and is capable of accepting data at eight times (n = 8 or 1.4 Mbytes/s) the
normal CD-ROM data rate.

Third level error correction hardware of SAA7385 is included to improve the correction efficiency of the system. The buffer manager hardware utilizes a ten-level arbitration unit and can stop the clock to the microcontroller to emulate a wait condition when necessary.

The SAA7385 comprises five major functional blocks:

· The 80C32 microcontroller is an industry standard core
· The 53CF94 is an industry standard core
· The front-end block connects to the external CD-60 based decoder and fully processes the incoming data stream to provide bytes of data that are stored in the external buffer
· The buffer manager block provides the address generation and timing control for the external DRAM buffer
· The ECC block performs the error correction functions in hardware on the data in the DRAM buffer.




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