Features: Serial Interface
` Eight independent full duplex serial channels
On chip clock generation or external clock source
On chip DPLL for clock recovery of each channel
Eight independent baud rate generators
Independent time-slot assignment for each channel with programmable time-slot length (1-256 bits)
` Async., sync. character oriented (MONOSYNC / BISYNC) or HDLC/SDLC modes (including SDLC LOOP)
` Transparent receive/transmit of data bytes without framing
` NRZ, NRZI, FM and Manchester encoding
` Modem control lines (RTS, CTS, CD)
` CRC support:
HDLC/SDLC: CRC-CCITT or CRC-32 (automatic handling for transmit/receive direction)
BISYNC: CRC-16 or CRC-CCITT (support for transmit direction)
` Support of bus configuration by collision detection and resolution
` Statistical multiplexing
` Continuous transmission of 1 to 32 bytes possible
` Programmable Preamble (8 bit) with selectable repetition rate (HDLC/SDLC and BISYNC)
` Data rate up to 10 Mbit/s
` Master clock mode with data rate up to 4 Mbit/s
Protocol Support (HDLC / SDLC)
` Various types of protocol support depending on operating mode
Auto mode (automatic handling of S and I frames)
Non-auto mode
Transparent mode
` Handling of bit oriented functions
` Support of LAPB / LAPD / SDLC / HDLC protocol in auto mode (I- and S-frame handling)
` Modulo 8 or modulo 128 operation
` Programmable time-out and retry conditions
` Programmable maximum packet size checking
MP Interface and Ports
` 64 byte FIFOs per channel and direction (byte or word access)
` 8/16 bit microprocessor bus interface (Intel or Motorola type)
` All registers directly accessible (byte and word access)
` Efficient transfer of data blocks from/to system memory via DMA or interrupt request
` Support of Daisy Chaining and Slave Operation with Interrupt Vector generation
` 28-bit programmable universal I/Os
General
` Advanced CMOS technology
` Low power consumption: active 200 mW at 2 MHz/standby 20 mW (typical values)
` P-MQFP-160 PackageApplication·Universal, multiprotocol communication boards
·Asynchronous and synchronous terminal cluster controllers
·LAN gateways and bridges
·Multiplexers, cross-connect points, DMI boards
·Time slotted packet networks
·Packet switches, packet assemblers/disassemblersPinout
SpecificationsSupply voltage VDD = 0.3 to + 7.0 V
Input voltage VI = 0.3 to VDD + 0.3 V (max. 7 V)
Output voltage V0 = 0.3 to VDD + 0.3 V (max. 7 V)
Storage temperature TSTG = 65 to + 150 °C
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to conditions beyond those indicated in the recommended operational conditions of this specification may affect device reliability.This is a stress rating only and functional operation of the device under these conditions or at any other condition beyond those indicated in the operational conditions of this specification is not implied.
DescriptionThe ESCC8 distinguishes itself from other communication controllers by its advanced characteristics. The most important are:
` Eight independent serial channels.
` Support of HDLC, SDLC, BISYNC/MONOSYNC and Asynchronous protocols.
` Support of layer-2 functions (HDLC mode).
In addition to those bit-oriented functions commonly supported by HDLC controllers,such as bit stuffing, CRC check, flag and address recognition, the ESCC8 provides a high degree of procedural support.
In a special operating mode (auto-mode), the ESCC8 processes the information transfer and the procedure handshaking (I- and S-frames of HDLC protocol) autonomously. The only restriction is that the window size (= number of outstanding unacknowledged frames) is limited to 1, which is sufficient for many applications. The communication procedures are mainly processed between the communication controllers and not between the attached processors. Thus the dynamic load on the CPU and the software expense is greatly reduced.
The SAF82538 CPU is informed about the status of the procedure and has mainly to manage the receive and transmit data. In order to maintain cost effectiveness and flexibility, the handling of unnumbered (U) frames, and special functions such as error recovery in case of protocol errors, are not implemented in hardware and must be done by the user's software.
` Extended support of different link configurations.
Besides the point-to-point configurations, the ESCC8 allows the implementation of point-to-multipoint or multi-master configurations without additional hardware or software expense.
In point-to-multipoint configurations, the ESCC8 can be used as a master or as a lave station. Even when working as slave station, the ESCC8 can initiate the transmission of data at any time. An internal function block provides means of idle and collision detection and collision resolution, which are necessary if several stations start transmitting simultaneously. Thus, a multi-master configuration is also possible.
` Telecom specific features.
In a special operating mode, the ESCC8 can transmit or receive data packets in one of up to 64 time-slots of programmable width (clock mode 5). Furthermore, the ESCC8 can transmit or receive variable data portions within a defined window of one or more clock cycles in conjunction with an external strobe signal (clock mode 1). These features make the ESCC8 suitable for applications using time division multiplex methods, such as time-slot oriented PCM systems or systems designed for packet switching.
` FIFO buffers for efficient transfer of data packets.
A further speciality of ESCC8 are the 64-byte deep FIFO buffers used for the temporary storage of data packets transferred between the serial communications interface and the parallel system bus. Because of the overlapping input/output operation (dual-port behaviour), the maximum message length is not limited by the size of the buffer. The dynamic load of the CPU is drastically reduced by transferring the data packets block by block via Direct Memory Access supported by the ESCC8. The CPU only has to initiate the data transmission by the ESCC8 and determine the status in case of completed reception, but is not involved in data transfers.
` The 16-bit wide microprocessor interface enables SAF82538 high data throughput and offers a high flexibility for connection to both 8/16-bit Siemens/Intel and Motorola type microprocessor systems. Moreover, interrupt driven systems are supported by vectored interrupts and interrupt cascading capabilities.
` In addition to SAF82538 standard modem control lines associated with each of the serial channels, 28 universal ports are provided for applications related to or independent of the serial channels.
SAF82538 Data Sheet
