SC32442 Features
* ARM920T CPU Core
• 64-way set-associative cache with :
- I-Cache (16 KB) and D-Cache (16 KB)
• Write-through and Write-back cache operation.
• MMU supports WinCE and LINUX.
Internal AMBA bus architecture (AMBA2.0, AHB/APB)
* Stacked Memory Configuration
• MCP1 : 256Mb mSDRAM (x32) + 512Mb NAND (x8)
• MCP2 : 256Mb mSDRAM (x32) + 1Gb NAND (x8)
• MCP3 : 512Mb mSDRAM (x32) + 1Gb NAND (x8)
• MCP4 : 512Mb mSDRAM (x32) + 2Gb NAND (x8)
• MCP5 : 512Mb mSDRAM (x32)
* System Manager
• Little/Big-Endian support
• Address space : 128MB for each bank (total 1GB)
• 8 memory banks :
- 6 memory banks for ROM, SRAM, and others
- 2 memory banks for ROM/SRAM/SDRAM
• NAND Flash Boot Loader
- 4 KB internal buffer for booting
- Supports storage memory after booting
• Power Manager : supports STOP/SLEEP/IDLE mode
* Operating Conditions
• Internal : 1.35/1.5V
• External I/O : 2.3~3.6V
• Speed : 300MHz @1.35V
400MHz @1.5V
• Memory : 1.8V
* On-chip Peripherals
• NAND Flash Controller (Normal/Advanced)
• LCD Controller (up to 4K color STN and 256K color TFT) with
1-ch LCD dedicated to DMA
• Camera Interface supporting up to 4096 x 4096 resolution
(2048 x 2048 pixel input support for scaling)
• USB Host/Device Interface
- 2 ports USB Host (Version 1.1 Compliant)
- 1 port USB Device (Version 1.1 Compliant)
• 4-ch DMA Controllers
• 3-ch UARTs with IrDA 1.0 (Including 64 byte FIFO)
• 1-ch multi-master I2C-Bus Interface
• 1-ch I2S-Bus Interface
• 4-ch 16 bit PWMs (Pulse Width Modulation) and 1-ch 16-bit
timer for OS
• 130 multiplexed GPIO ports
• 8-ch 10-bit ADCs (Max. 500KSPS), including TSP Controller
• 16-bit Watch-dog Timer
• RTC with calendar function
• On-chip clock generator with PLL
• 2-ch SPIs (Synchronous Serial I/O)
• SD Host/MMC (Multimedia Card) Interface
• Debug and TEST
* Package
• 332 FBGA 14 X 14
SC32442 Typical Application
• PDA/Smart Phone
• Car Navigation
• Portable Game Player
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