Features: IEEE 1149.1 (JTAG) Compliant Buffered positive edge-triggered clock 3-STATE outputs for bus-oriented applications 9-bit data busses for parity applications Reduced-swing outputs source 32 mA/sink 64 mA Guaranteed to drive 50 transmission line to TTL input levels of 0.8V and 2.0V TTL com...
SCAN18374T: Features: IEEE 1149.1 (JTAG) Compliant Buffered positive edge-triggered clock 3-STATE outputs for bus-oriented applications 9-bit data busses for parity applications Reduced-swing outputs source 32...
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Interface Development Tools SCAN15MB200 EVAL BOARD

The SCAN18374T consists of two sets of nine edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable pins are common to all flip-flops. Each set of the nine flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (ACP or BCP) transition. With the Output Enable (AOE1 or BOE1) LOW, the contents of the nine flip-flops are available at the outputs. When the Output Enable is HIGH, the outputs go to the high impedance state. Operation of the Output Enable input does not affect the state of the flip-flops.