SH7708 Series

      This is the description of SH7708 Series:
      The SH7708, SH7708S, and SH7708R (SH7708 Series) are 32-bit RISC (reduced instruction set computer) microcomputers, featuring object code upward-compatibility with SH-1 and SH-2 microcomputers. The SH7708R is completely pin compatible with the SH7708S. It includes an 8- Kbyte cache with a choice of write-back or write-through mode, and an MMU (memory management unit) with a 128-entry 4-way set associative TLB (translation look aside buffer).
The SH7708 Series have an on-chip bus state controller (BSC) that allows direct connection to DRAM, synchronous DRAM (SDRAM), and pseudo-SRAM (PSRAM) without external circuitry. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.
      And these are the features of SH7708 Series: the first one is Original Hitachi SuperH RISC engine architecture. The second one is 32-bit internal data bus. The third one is General-register machine, which are: firstly, Sixteen 32-bit general registers (eight 32-bit bank registers), secondly, Five 32-bit control registers, thirdly, Four 32-bit system registers. And the forth one is RISC-type instruction set (upward compatibility with the SH-1 and SH-2 series), which including: firstly, Instruction length: 16-bit fixed length for improved code efficiency. Secondly, Load-store architecture. Thirdly, Delayed branch instructions. Fourthly, C-oriented instruction set. The fifth one is Instruction execution time: one instruction/cycle for basic instructions. And the sixth one is Logical address space: 4 Gbytes (448-Mbyte actual memory space). The seventh one is Space identifier ASID: 8 bits, 256 logical address spaces. The eighth one is On-chip multiplier. And the last one is  Five-stage pipeline.