SK100E131

The SK10E/100E131 is a Quad master-slave D-type flipflop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CE*) inputs for clocking. Common clocking is achieved by holding the CE inputs LOW and using CC to clock all four flip-flops. In this case, the CE* inputs perform the function of controlling the common clock to each flip-flop.

Individual asynchronous resets of SK10E/100E131 are provided (R). Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry.

Data enters the master when both CC and CE* are LOW, and transfers to the slave when either CC or CE (or both) go HIGH.