SL23EP08

The SL23EP08 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to eight (8) clock outputs from one (1) reference input clock, for high speed clock distribution applications.

The product has an on-chip PLL and a feedback pin (FBK) which can be used to obtain feedback from any one of the output clocks. The SL23EP08 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, bank-B output clock buffers can be tri-stated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the SL23EP08 behave like a Non-Zero Delay Buffer (NZDB). The SL23EP08 offers various X/2,1X, 2X and 4x frequency options at the output clocks. Refer to the "Product Configuration Table" for the details.

The SL23EP08-1H, -2H and 5H versions operates up to 220 MHz and SL23EP08-1, -2, -3 and -4 versions operate up to 133 MHz with CL=15pF output load.