Features: · Operating Voltage Range: 3.0 to 18 V· Maximum input current of 1 mA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C· Noise margin (over full package temperature range):-1.0 V min @ 5.0 V supply-2.0 V min @ 10.0 V supply-2.5 V min @ 15.0 V supplyPinoutSpecifications ...
SL4034B: Features: · Operating Voltage Range: 3.0 to 18 V· Maximum input current of 1 mA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C· Noise margin (over full package temperature range...
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| Symbol | Parameter |
Value |
Unit |
| VCC | DC Supply Voltage (Referenced to GND) |
-0.5 to +20 |
V |
| VIN | DC Input Voltage (Referenced to GND) |
-0.5 to VCC +0.5 |
V |
| VOUT | DC Output Voltage (Referenced to GND) |
-0.5 to VCC +0.5 |
V |
| IIN | DC Input Current, per Pin |
±10 |
mA |
| PD | Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ |
750 500 |
mW |
| PD | Power Dissipation per Output Transistor |
100 |
mW |
| Tstg | Storage Temperature |
-65 to +150 |
°C |
| TL | Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) |
260 |
°C |
The SL4034B is a static eight-stage parallel-or serial-input paralleloutput register. It can be used to: 1) bidirectionally transfer parallel information between two buses, 2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Inputs that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/ B-BUS-TO-A-BUS (A/B), and ARALLEL/SERIAL (P/S).
Data inputs of the SL4034B include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) dependung on the signal level on the A/B input. In addition, an input for SERIAL DATA is also provided.
All register stages of the SL4034B are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave.