Features: · Outputs Directly Interface to CMOS, NMOS, and TTL· Operating Voltage Range: 2.0 to 6.0 V· Low Input Current: 1.0 mA· High Noise Immunity Characteristic of CMOS DevicesPinoutSpecifications Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +...
SL74HC651: Features: · Outputs Directly Interface to CMOS, NMOS, and TTL· Operating Voltage Range: 2.0 to 6.0 V· Low Input Current: 1.0 mA· High Noise Immunity Characteristic of CMOS DevicesPinoutSpecification...
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| Symbol | Parameter |
Value |
Unit |
| VCC | DC Supply Voltage (Referenced to GND) |
-0.5 to +7.0 |
V |
| VIN | DC Input Voltage (Referenced to GND) |
-1.5 to VCC +1.5 |
V |
| VOUT | DC Output Voltage (Referenced to GND) |
-0.5 to VCC +0.5 |
V |
| IIN | DC Input Current, per Pin |
±20 |
mA |
| IOUT | DC Output Current, per Pin |
±35 |
mA |
| Icc | DC Supply Current, VCC and GND Pins |
±75 |
mA |
| PD | Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ |
750 500 |
mW |
| Tstg | Storage Temperature |
-65 to +150 |
°C |
| TL | Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) |
260 |
°C |
The SL74HC651 is identical in pinout to the LS/ALS651. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
These devices SL74HC651 consists of bus transceiver circuits, D-type flip-flop, and control circuitry arranged for multiplex transmission of data directly from the data bus or from the internal storage registers. Direction and Output Enable are provided to select the read-time or stored data function. Data on the A or B Data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (A-to-B Clock or B-to-A Clock) regardless of the select or enable or enable control pins. When A-to-B Source and B-to- A Source are in the real-time transfer mode, it is als o possible to store data without using the internal D-type flip-flops by simulta-neously enabling Direction and Output Enable. In SL74HC651 configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.