SL74HCT138

Features: · TTL/NMOS Compatible Input Levels· Outputs Directly Interface to CMOS, NMOS, and TTL· Operating Voltage Range: 4.5 to 5.5 V· Low Input Current: 1.0 mAPinoutSpecifications Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V VIN DC...

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SeekIC No. : 004492735 Detail

SL74HCT138: Features: · TTL/NMOS Compatible Input Levels· Outputs Directly Interface to CMOS, NMOS, and TTL· Operating Voltage Range: 4.5 to 5.5 V· Low Input Current: 1.0 mAPinoutSpecifications Symbol Par...

floor Price/Ceiling Price

Part Number:
SL74HCT138
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/25

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Product Details

Description



Features:

·  TTL/NMOS Compatible Input Levels
·  Outputs Directly Interface to CMOS, NMOS, and TTL
·  Operating Voltage Range: 4.5 to 5.5 V
·  Low Input Current: 1.0 mA



Pinout

  Connection Diagram


Specifications

Symbol Parameter
Value
Unit
VCC DC Supply Voltage (Referenced to GND)
-0.5 to +20
V
VIN DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
VOUT DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN DC Input Current, per Pin
±20
mA
IOUT DC Output Current, per Pin
±25
mA
Icc DC Supply Current, VCC and GND Pins
±50
mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg Storage Temperature
-65 to +150
°C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
°C



Description

The SL74HCT138 is identical in pinout to the LS/ALS138. The SL74HCT138 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

The SL74HCT138 decodes a three-bit Address to one-of-eight active-lot outputs. This device features three Chip Select inputs, two active-low and one active-high to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states.




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