SLA7062MLF2102

• To 3 A Output Rating
• Internal Sequencer for Microstepping Operation
• PWM Constant-Current Motor Drive
• Cost-Effective, Multi-Chip Solution
• 100 V, Avalanche-Rated NMOS Outputs
• Low rDS(on) NMOS Outputs (150 milli-ohms typical)
• Advanced, Improved Body Diodes
• Inputs Compatible with 3.3 V or 5 V Control Signals
• Sleep Mode
• Internal Clamp Diodes

Combining low-power CMOS logic with high-current, high-voltage power FET outputs, the Series SLA7060M translator/drivers provide complete control and drive for a two-phase unipolar stepper motor with internal fixed off time and pulse-width modulation (PWM) control of the output current in a power multi-chip module (PMCMT). There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program.

The CMOS logic section provides the sequencing logic, direction, control, synchronous/asynchronous PWM operation, and a "sleep" function. The minimum CLOCK input is an ideal fit for applications where a complex P is unavailable or overburdened. TTL or LSTTL may require the use of appropriate pull-up resistors to ensure a proper input-logic high. For PWM current control, the maximum output current is determined by the user&primes selection of a reference voltage and sensing resistor. The NMOS outputs are capable of sinking up to 1, 2, or 3 A (depending on device) and withstanding 46 V in the off state. Clamp diodes provide protection against inductive transients. Special power-up sequencing is not required.

Half-, quarter-, eighth-, and sixteenth-step operation are externally selectable for the SLA7060/61/62M. Half-step excitation alternates between the one-phase and two-phase modes (A-AB-B-AB-A-AB-B-AB), providing an eight-step sequence.

Description

Combining low-power CMOS logic with high-current, high-voltage power FET outputs, the Series SLA7062MLF2102 translator/drivers provide complete control and drive for a two-phase unipolar stepper motor with internal fixed off time and pulse-width modulation (PWM) control of the output current in a power multi-chip module (PMCMT). There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program.

The CMOS logic section SLA7062MLF2102 provides the sequencing logic, direction, control, synchronous/asynchronous PWM operation, and a "sleep" function. The minimum CLOCK input is an ideal fit for applications where a complex P is unavailable or overburdened. TTL or LSTTL may require the use of appropriate pull-up resistors to ensure a proper input-logic high. For PWM current control, the maximum output current is determined by the user&primes selection of a reference voltage and sensing resistor. The NMOS outputs are capable of sinking up to 1, 2, or 3 A (depending on device) and withstanding 46 V in the off state. Clamp diodes provide protection against inductive transients. Special power-up sequencing is not required.

Half-, quarter-, eighth-, and sixteenth-step operation are externally selectable for the SLA7060/61/SLA7062MLF2102. Half-step excitation alternates between the one-phase and two-phase modes (A-AB-B-AB-A-AB-B-AB), providing an eight-step sequence.