SN100KT5574

This SN100KT5574 octal ECL-to-TTL translator is designed to provide efficient translation between a 100K ECL signal environment and a TTL signal environment.

SN100KT5574  is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The eight flip-flops of the SN100KT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs.

A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off.The SN100KT5574 is characterized for operation from 0°C to 85°C.