SN54376

The SN54376 quadruple TTL J-K flip-flop incorporates a number of third-generation IC features that can simplify system design and reduce flip-flop package count by as much as design and reduce flip-flop package count by as much as 50%.It features hysteresis at the clock input, fully buffered outputs and direct clear capability.

Features of of the SN54376 are:(1)four J-K flip-flop in a single package can reduce FF package count by 50%; (2)common positive-edge-triggered clocks with hysteresis: typically 200 mV; (3)fully buffered outputs; (4)typical clock input frequency:45 MHz.