PinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 VInput voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 ...
SN54ABT16501: PinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 VInput voltage range, VI (exc...
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Features: PinoutSpecificationsDescriptionThe SN54/74LS147 and SN54/74LS148 are Priority Encoders. ...
PinoutDescriptionThe LS155 and LS156 are Dual 1-of-4 Decoder/Demultiplexers with common Address in...

Supply voltage range, V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V I (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . ..... 0.5 V to 5.5 V
Current into any output in the low state, IO : SN54ABT16501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT16501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .....128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, q JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . ......... . . . . . . . . . . . . . 81 /W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... . 74 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150
These SN54ABT16501 18-bit universal bus transceivers consist of storage elements that can operate either as D-type latches or D-type flip-flops to allow data flow in transparent or clocked modes.
Data flow in each direction of SN54ABT16501 is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output of SN54ABT16501 enables are complementary (OEAB is active high and OEBAis active low). To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor and OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing/current-sinking capability of the driver.