SN54ABT16623

Features:

 Members of the Texas Instruments Widebus^tm Family
 State-of-the-Art EPIC-IIB^tm BiCMOS Design Significantly Reduces Power Dissipation
 Latch-Up Performance Exceeds 500 mA Per  JEDEC Standard JESD-17
 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
 Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
 Flow-Through Architecture Optimizes PCB Layout
 High-Drive Outputs (32-mA IOH, 64-mA IOL)
 Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink
 Small-Outline (DGG) Packages and 380-mil
 Fine-Pitch Ceramic Flat (WD) Package
 Using 25-mil Center-to-Center Spacings


Pinout




Specifications

Supply voltage range, V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V_I (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V_O  . . . 0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT16623 . . . . . . . . . . . . . . . . . . . 96 mA
                                                                 SN74ABT16623  . . . . . . . . . . . . . . . . . . . . .128 mA
Input clamp current, I_IK (V_I < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, q_JA (see Note 2): DGG package.. . . . . . . .. . . . . . ... . . 89°C/W
                                                                          DL package. . . . . . . . . . . . . . . . . . . . 94°C/W
Storage temperature range, T_stg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C


Description

The SN54ABT16623  are 16-bit transceivers designed for asynchronous communication between data buses. The control-function implementation allows for maximum flexibility in timing. The SN54ABT16623 provide true data at the outputs.

These SN54ABT16623 devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic levels at the output-enable (OEAB and OEBA) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.The dual-enable configuration gives the transceivers the capability of storing data by simultaneously enabling OEBA and OEBA. Each output reinforces its input in this configuration.When both OEAB and OEBA are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (32 total) remain at their last states.