SN54ABT16833

Features:

 Members of the Texas Instrumenst Widebus^tm Family
 State-of-the-Art EPIC-IIBE BiCMOS Desing Significantly Reduces Power Dissipation
 Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
 Typical VOLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
 Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
 Flow-Through Architecture Optimizes PCB Layout
 High-Drive Outputs (32-mA IOH, 64-mA IOL)
 Parity-Error Flag With Parity Generator/Checker
 Register for Storage of Parity-Error Flag
 Package Options Include Plastic 300-mil
 Shrink Small-Outline (DL) and Thin Shrink
 Small-Outline (DGG) Packages and 380-mil
 Fine-Pitch Ceramic Flat (WD) Package
 Using 25-mil Center-to-Center Spacings


Application

Audio                             www.ti.com/audio
Automotive                    www.ti.com/automotive
Broadband                     www.ti.com/broadband
Digital Control                www.ti.com/digitalcontrol
Military                           www.ti.com/military
Optical Networking        www.ti.com/opticalnetwork
Security                         www.ti.com/security
Telephony                     www.ti.com/telephony
Video & Imaging            www.ti.com/video
Wireless                        www.ti.com/wireless


Pinout




Description

The 'ABT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY). When data of 'ABT16833 is transmitted from the B bus to the A bus, 1PARITY (or 2PARITY) is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected.

The error (1ERR or 2ERR) output of 'ABT16833 is configured as an open-collector output. The B-to-A parity-error flag is clocked into 1ERR (or 2ERR) on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR (or 2ERR) is cleared (set high) by taking the clear (1CLR or 2CLR) input low.