SN54ABT240

Features: • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17• Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C• High-Drive Outputs (32-mA IOH, 64-mA IOL)...

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SeekIC No. : 004496319 Detail

SN54ABT240: Features: • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17• Typical VOLP (Output...

floor Price/Ceiling Price

Part Number:
SN54ABT240
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Features:

• State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
• High-Drive Outputs (32-mA IOH, 64-mA IOL)
• Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), and Plastic (N) and Ceramic (J) DIPs






Pinout

  Connection Diagram




Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Voltage applied to any output in the high state or power-off state, VO . . . . . . . . . .0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT240 . . . . . . . . . . . . .. . . . . . . . . . . . .. . .96 mA
SN74ABT240 . . . . . . . . . . . . . . . . . . . . . . . . . .128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. .18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . .0.6 W
DW package . . . .. . . . . .. .1.6 W
N package . . . . . . . . . . . . . .1.3 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .65°C to 150°C





Description

These SN54ABT240 octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Taken together with the 4ABT241 and 4ABT244, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE) inputs, and complementaryOE and OE inputs.

The SN54ABT240 is organized as two 4-bit buffers/line drivers with separateOE inputs. WhenOE is low, the device passes data from the A inputs to the Y outputs. WhenOE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down,OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.The SN74ABT240 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54ABT240 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT240 is characterized for operation from 40°C to 85°C.






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