SN54ABT574

Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to 7 V
Input voltage range, V_I (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V_O  . . . . . . . .
                                                                      . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V
Current into any output in the low state, I_O : SN54ABT574   . . . .. . . . . . . . . .96 mA 
                                                                        SN74ABT574A . . . . . . . . . . . . 128 mA
Input clamp current, I_IK (V_I< 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-18 mA
Output clamp current, I_OK(V_O < 0)   . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .-50 mA
Package thermal impedance, JA(see Note 3): DB package  . . . . . . . . . . . . .  70/W
                                                   (see Note 3): DW package  . . . . . .. . . . . . .  58/W
                                                   (see Note 3): DQN/ZQN package  . . . . . .  . . 78/W
                                                   (see Note 3): N package      . . . . .  . . . . . . .  69/W
                                                   (see Note 3): NS package  . . . . . . . . . . . . . .  60/W
                                                   (see Note 3): PW package  . . . . .. . . . . . . . .  83/W
                                                   (see Note 4): RGY package  . . . . . . . . .. . . . . 37/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .-65 to 150


Description

These 8-bit flip-flops feature 3-state outputs of SN54ABT574 and SN74ABT574A designed specifically for driving highly capacitive or relatively low-impedance loads. SN54ABT574 and SN74ABT574A are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the SN54ABT574 and SN74ABT574A are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.