SN54AC74

· EPIC^TM (Enhanced-Performance Implanted CMOS) 1-mm Process
· Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Flat (W), and DIP (J,N) Packages

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V_CC + 0.5 V
Output voltage range, V_O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (VI < 0 or V_I > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . ±20 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . ±50 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . ±200 mA
Maximum power dissipation at T_A = 55°C (in still air) (see Note 2): D package . . . . . . .  . . . 1.25 W
                                                                                                          DB package . . . . . .  . . . . 0.5 W
                                                                                                          N package . . . . . . . . .. . . 1.1 W
                                                                                                          PW package . . . . . . . . . . 0.5 W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.

The 'AC74 are dual positive-edge-triggered D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

The SN54AC74 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AC74 is characterized for operation from 40°C to 85°C.