SN54ACT533

·􀀀 Inputs Are TTL-Voltage Compatible
·􀀀 3-State Inverting Outputs Drive Bus Lines Directly
·􀀀 EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process
·􀀀 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic (N) and Ceramic (J) DIPs

Supply voltage range, V_CC . . . . . . . . . . . . . . .  . . . . . . . . . 0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . 0.5 V to V_CC + 0.5 V
Output voltage range, V_O (see Note 1) . . . . . . . . 0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0 or V_I > V_CC) . . . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) . .   . . . . . . . . . . ±20 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . .  . .  . . . . . ±50 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, _JA (see Note 2): DB package . . . . 70°C/W
                                                                           DW package . . . 58°C/W
                                                                           N package . . . . . 69°C/W
                                                                           PW package . .  . 83°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . .  . 65°C to 150°C

‡ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.

The SN54ACT533 devices are octal transparent D-type latches with 3-state outputs. When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverted levels set up at the D inputs.

A buffered output-enable (OE) input of SN54ACT533 can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs of SN54ACT533 neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect the internal operations of the latches. Old data of SN54ACT533 can be retained or new data can be entered
while the outputs are in the high-impedance state.

The SN54ACT533 is characterized for operation over the full military temperature range of 55°C to 125°C. The
SN74ACT533 is characterized for operation from 40°C to 85°C.