Features: ·D-Type Flip-Flops in a Single Package With 3-State Bus Driving True Outputs·Full Parallel Access for Loading·Buffered Control Inputs·Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPsPinoutSpecifications...
SN54ALS374A: Features: ·D-Type Flip-Flops in a Single Package With 3-State Bus Driving True Outputs·Full Parallel Access for Loading·Buffered Control Inputs·Package Options Include Plastic Small-Outline (DW) Pac...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Features: PinoutSpecificationsDescriptionThe SN54/74LS147 and SN54/74LS148 are Priority Encoders. ...
PinoutDescriptionThe LS155 and LS156 are Dual 1-of-4 Decoder/Demultiplexers with common Address in...

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . .. .. 0.5 V to 7 V
Voltage applied to a disabled 3-state output . . . . . . . . 0.5 V to 5.5 V
Package thermal impedance,JA (see Note 1): DW package . .. . 58/W
N package . . . . . 69/W
Storage temperature range, Tstg . .. . .. .. .. .. .. .. .. .. . . . 65to 150
‡ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
These octal D-type edge-triggered flip-flops of SN54ALS374A and SN54AS374 feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. SN54ALS374A and SN54AS374 are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs of SN54ALS374A and SN54AS374 are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input places the eight outputs of SN54ALS374A and SN54AS374 in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect internal operations of the flip-flops. Old data of SN54ALS374A and SN54AS374 can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range
of 55 to 125. The SN74ALS374A and SN74AS374 are characterized for operation from 0 to 70.