SN54HC163

Features:

Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-A Max ICC
Typical t  = 14 ns
pd ±4-mA Output Drive at 5 V
Low Input Current of 1 A Max
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
Synchronously Programmable


Pinout




Specifications

Supply voltage range, V_CC   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..  -0.5 V to 7 V
Input clamp current, I_IK  (V_I < 0 or V_I > V _CC ) (see Note 1)  . . . . . . . . . .  . . . . . . .  ±20 mA
Output clamp current, I_OK  (V_O  < 0 or V_O  > V_CC ) (see Note 1)  . . . . . . . . . . . . . .  ± 20 mA
Continuous output current, I_O  (V_O  = 0 to V_CC )  . . . . . . . . . . . . . . . . . . . . . . . . . .  ± 25 mA
Continuous current through V_CC  or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±50 mA
Package thermal impedance, JA (see Note 2): D package  . . . .. . . . . . . . . . . . . . .  73°C/W
                                                                           DB package  . . . . . . . . .  . . . . . . . .  82°C/W
                                                                           N package  . . . . . . .  . . . . . . . . . . .  67°C/W
                                                                           NS package  . . . . . . . .. . . . . . . . . .  64°C/W
                                                                           PW package  . . . .  . . . . . . . . . . . . 108°C/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . -65° C to 150° C
 

Description

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The 'HC163 devices are 4-bit binary counters. Synchronous operation 'HC163 is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when
instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation 'HC163 eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.