SN54HC273

Application

− Buffer/Storage Registers
− Shift Registers
− Pattern Generators


Pinout




Specifications

Supply voltage range, V_CC .. . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I_IK (VI < 0 or VI > V_CC) (see Note 1) .. . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or VO > V_CC) (see Note 1) . ±20 mA
Continuous output current, I_O (V_O = 0 to V_CC) .  . . . . . . . . . . . ±25 mA
Continuous current through V_CC or GND .. . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, JA (see Note 2): DB package . . 70°C/W
                                                                          DW package . . 58°C/W
                                                                          N package  . . . 69°C/W
                                                                          NS package .. . 60°C/W
                                                                          PW package . . 83°C/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . −65°C to 150°C

Description

These circuits of SN54HC273 are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input.

Information at the data (D) inputs SN54HC273 meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK SN54HC273 is at either the high or low level, the D input has
no effect at the output.