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Part Number: SN54LS148
Description: These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is en...
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SN54LS148
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General Description
SN54LS148 General Description
These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The '147 and 'LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.
The '148 and 'LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent one normalized Series 54/74 or 54/74LS load, respectively.
SN54LS148 Maximum Ratings
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
Input voltage, VI: '147, '148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..5.5 V
'LS147, 'LS148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
Inter-emitter voltage: '148 only (see Note 2) . . . . . . . . . . . . . . . . . . . . . .5.5 V
Package thermal impedance JA (see Note 3): D package . . . . . . . . . .73°C/W
N package . . . . . . . . . ..67°C/W
NS package . . . . . . . 64°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . .−65°C to 150°C
Input voltage, VI: '147, '148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..5.5 V
'LS147, 'LS148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
Inter-emitter voltage: '148 only (see Note 2) . . . . . . . . . . . . . . . . . . . . . .5.5 V
Package thermal impedance JA (see Note 3): D package . . . . . . . . . .73°C/W
N package . . . . . . . . . ..67°C/W
NS package . . . . . . . 64°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . .−65°C to 150°C
SN54LS148 Typical Application
Audio
Automotive
Broadband
Digital Control
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
SN54LS148 Connection Diagram
SN54LS148
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- Datasheet: SN54LS148
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- ·SN54/74LS00
- QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY
- 34868 KB
- ·SN54/74LS01
- QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY
- 33930 KB
- ·SN54/74LS02
- QUAD 2-INPUT NOR GATE
- 36438 KB
- ·SN54/74LS03
- QUAD 2-INPUT NAND GATE
- 33910 KB
- ·SN54/74LS04
- HEX INVERTER
- 35052 KB
- ·SN54/74LS05
- HEX INVERTER
- 34028 KB
- ·SN54/74LS08
- QUAD 2-INPUT AND GATE
- 34431 KB
- ·SN54/74LS09
- QUAD 2-INPUT AND GATE
- 33463 KB
SN54LS148 Relative Products
SN54LS147
These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The '147 and 'LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condit...
SN54LS145
The SN54LS145 is one of the SN54145 series.The SN54LS145 is a monolithic,this monolithic BCD-to-decimal decoder/drivers consist of eight inverters and ten four-input NAND gates.The inverters are connected in pairs to make BCD input data available for decodin...
SN54LS14
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SN54LS139A
The Schottky-calmped TTL MSI circuit SN54LS139A is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times.In high-performance memory systems, SN54LS139A can be used to minimize the ef...
SN54LS138
The Schottky-clamped TTL MSI circuit SN54LS138 is designed to be used in high-performance memory deconding or data-routing applications requiring very short propagation delay times.In high-performance memory systems, SN54LS138 can be used to minimize the eff...
SN54LS137
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