SN54LS173A

The '173 and 'LS173A 4-bit registers include -type flip-flops featuring totem-pole 3-state utputs capable of driving highly capacitive r relatively low-impedance loads. The igh-impedance third state and increased igh-logic-level drive provide these flip-flops with he capability of being connected directly to and riving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of he SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or 4LS/74LS TTL normalized loads, espectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can e connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load, espectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic ,vels, the output control circuitry is designed so that the average output disable imes are shorter than the verage output enable times.

Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both ata-enable (G1 , G2) inputs are low, data at the D inputs are loaded into heir respective flip-flops on the next ositive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both re low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus
nes. The outputs are disabled independently from the level of the clock by a high logic level at eitheroutput-control input. The outputs then present a high impedance and neither load nor rive the bus line. Detailed peration is given in the function table.

The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of
55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.