SN54LV165

Supply voltage range, V_CC  . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .0.5 V to 4.6 V
Input voltage range, V_I (see Note 1) . . . . . . .. . . . . . . . . . . . . . . . . . . . .0.5 V to VCC + 0.5 V
Output voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . .0.5 V to VCC + 0.5 V
Input clamp current, I_IK (V_I < 0 or V_I > V_CC)  . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC)  . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V_CC or GND. . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .±50 mA
Maximum power dissipation at T_A = 55 (in still air) (see Note 3): D package  . . . . . . . . .1.30 W
                                                                                                        DB package  . . . . . . . .0.55 W
                                                                                                        PW package . . . .. . . . . 0.5 W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .65 to 150

The 'LV165 parallel-load, 8-bit shift registers aredesigned for 2.7-V to 5.5-V V_CC operation.
When the SN54LV165 is clocked, data is shifted towardthe serial output Q_H. Parallel-in access to eachstage is provided by eight individual direct datainputs that are enabled by a low level at the SH/LDinput. The 'LV165 feature a clock inhibit functionand a complemented serial output QH.
Clocking is accomplished by a low-to-hightransition of the clock (CLK) input while SH/LD isheld high and clock inhibit(CLK INH) is held low. The functions of the CLK and CLK INH SN54LV165 inputs areinterchangeable. Since a low CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLKINH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is heldhigh. The parallel inputs to the register are enabled while SH/LD is held low independently of the levels of CLK,CLK INH, or SER.
The SN54LV165 is characterized for operation over the full military temperature range of 55to 125. The SN74LV165 is characterized for operation from 40 to 85