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SN54LV165A

Features: *2-V to 5.5-V VCC Operation* Max tpd of 10.5 ns at 5 V* Support Mixed-Mode Voltage Operation on All Ports* Ioff Supports Partial-Power-Down Mode Operation* Latch-Up Performance Exceeds 250 mA Per JESD 17* ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200...

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SeekIC No. : 004497071 Detail

SN54LV165A: Features: *2-V to 5.5-V VCC Operation* Max tpd of 10.5 ns at 5 V* Support Mixed-Mode Voltage Operation on All Ports* Ioff Supports Partial-Power-Down Mode Operation* Latch-Up Performance Exceeds 250...

SN54LV165A Data Sheet

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Part Number:
SN54LV165A
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Product Details

Description



Features:

* 2-V to 5.5-V VCC Operation
*  Max tpd of 10.5 ns at 5 V
*  Support Mixed-Mode Voltage Operation on
    All Ports
*  Ioff Supports Partial-Power-Down Mode
    Operation
*  Latch-Up Performance Exceeds 250 mA Per
    JESD 17
*  ESD Protection Exceeds JESD 22
    − 2000-V Human-Body Model (A114-A)
    − 200-V Machine Model (A115-A)
    − 1000-V Charged-Device Model (C101)


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .−0.5 V to 7 V
Input voltage range, VI (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .−0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−0.5 V to 7 V
Output voltage range, VO (see Notes 1 and 2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−20 mA
Output clamp current, IOK (VO < 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .±50 mA
Package thermal impedance, JA (see Note 3): D package  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .73/W
                                                    (see Note 3): DB package  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . .82/W
                                                    (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... . .120/W
                                                    (see Note 3): NS package  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . .67/W
                                                    (see Note 3): PW package  . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . .108/W
                                                    (see Note 4): RGY package  . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . .39/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . .−65 to 150


Description

The 'LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.

When the LV165A is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The 'LV165A devices feature a clock-inhibit function and a complemented serial output, QH.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH LV165A should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are enabled while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.

LV165A is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.




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