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SN54LVT646

Features: · State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation· Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)· Support Unregulated Battery Operation Down to 2.7 V· Typical VOLP (Output Ground Bounce...

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SeekIC No. : 004497170 Detail

SN54LVT646: Features: · State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation· Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3...

SN54LVT646 Data Sheet

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Part Number:
SN54LVT646
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· State-of-the-Art Advanced BiCMOS
  Technology (ABT) Design for 3.3-V
  Operation and Low Static Power Dissipation
· Support Mixed-Mode Signal Operation (5-V
  Input and Output Voltages With 3.3-V VCC)
· Support Unregulated Battery Operation
  Down to 2.7 V
· Typical VOLP (Output Ground Bounce)
  < 0.8 V at VCC = 3.3 V, TA = 25°C
· ESD Protection Exceeds 2000 V Per
  MIL-STD-883C, Method 3015; Exceeds
  200 V Using Machine Model
  (C = 200 pF, R = 0)
· Latch-Up Performance Exceeds 500 mA
  Per JEDEC Standard JESD-17
· Bus-Hold Data Inputs Eliminate the Need
  for External Pullup Resistors
· Support Live Insertion
· Package Options Include Plastic
  Small-Outline (DW), Shrink Small-Outline
  (DB), and and Thin Shrink Small-Outline
  (PW) Packages, Ceramic Chip Carriers
  (FK), Ceramic Flat (W) Packages, and
  Ceramic (JT) DIPs


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . 0.5 V to 7 V
Current into any output in the low state, IO: SN54LVT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 mA
Current into any output in the high state, IO (see Note 2): SN54LVT646 . . . . . . . . . . . . . . . . . . . . . . . . .48 mA
SN74LVT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . .0.65 W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.


Description

These bus transceivers and registers LVT646 are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The 'LVT646 consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers LVT646 on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 4LVT646.

Output-enable (OE) and direction-control (DIR) inputs of LVT646 are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high), A data LVT646 may be stored in one register and/or B data may be stored in the other register.

When an output function of LVT646 is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time.




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