SN65LVDS1212

The SN65LVDS1021 serializer and SN65LVDS1212 deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes, at equivalent parallel word rates from 10 MHz to 40 MHz. SN65LVDS1021 and SN65LVDS1212 including overhead, this translates into a serial data rate between 120 Mbps and 480 Mbps payload-encoded throughput.

Upon power up, the chipset link SN65LVDS1021 and SN65LVDS1212 can be initialized via a synchronization mode with internally generated SYNC patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer SN65LVDS1021 and SN65LVDS1212 establishes lock within specified, shorter time parameters.

The SN65LVDS1021 and SN65LVDS1212 can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LVDS1021 and SN65LVDS1212 are characterized for operation over ambient air temperature of 40°C to 85°C.