SN65LVDS1224

`300660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock
`Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224
`Chipset (Serializer/Deserializer) Power Consumption <400 mW (Typ) at 66 MHz
`Synchronization Mode for Faster Lock
`Lock Indicator
`No External Components Required for PLL
`Low-Cost 28-Pin SSOP Package
`Industrial Temperature Qualified, T_A = 40°C to 85°C
`Programmable Edge Trigger on Clock
`Flow-Through Pinout for Easy PCB Layout

The SN65LVDS1023 serializer and SN65LVDS1224 deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes, at equivalent parallel word rates from 30 MHz to 66 MHz. Including overhead, this translates into a serial data of SN65LVDS1023 and SN65LVDS1224 rate between 360 Mbps and 792 Mbps payload encoded throughput.

Upon power up, the chipset link SN65LVDS1023 and SN65LVDS1224 can be initialized via a synchronization mode with internally generated SYNC patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer SN65LVDS1023 and SN65LVDS1224 establishes lock within specified, shorter time parameters.

The SN65LVDS1023 and SN65LVDS1224 can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LVDS1023 and SN65LVDS1224 are characterized for operation over ambient air temperature of 40°C to 85°C.