SN74ACT7206L

These SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, and SN74ACT7206L  devices are constructed with dual-port SRAM and have internal write and read address counters to provide data throughput on a first-in, first-out (FIFO) basis. Write and read operations are independent and can be asynchronous or  coincident. Empty and full status flags prevent underflow and overflow of memory, and depth-expansion logic allows combining the storage cells of two or more devices into one FIFO. Word-width expansion is also possible.

Data of SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, and SN74ACT7206L  is loaded into memory by the write-enable (W) input and unloaded by the read-enable (R) input. Read and write cycle times of 25 ns (40 MHz) are possible with data access times of 15 ns.

These SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, and SN74ACT7206L  devices are particularly suited for providing a data channel between two buses operating at asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in data-acquisition systems,  mporary storage elements between buses and magnetic or optical memories, and queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for retransmitting previously read data when a device is not used in depth expansion.

The SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, and SN74ACT7206L are characterized for operation from 0°C to 70°C.