SN74AHCT1G02

·􀀀 EPICE^TM (Enhanced-Performance Implanted CMOS) Process
·􀀀 Inputs Are TTL-Voltage Compatible
·􀀀 Latch-Up Performance Exceeds 250 mA Per JESD 17
·􀀀 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
·􀀀 Package Options Include Plastic Small-Outline Transistor (DBV, DCK) Packages

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . .  . . . . 0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . .  . . . . 0.5 V to 7 V
Output voltage range, V_O (see Note 1) . . . . . . . . . . . 0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . .. . . . . . 20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) . . . . . . . .  . . . . . . . ±20 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . .. . . . . . . . . ±25 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . .. . . . . ±50 mA
Package thermal impedance, JA (see Note 2): DBV package . . . . 347°C/W
                                                                          DCK package . .. . . 389°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . 65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are  bserved.
2. The package thermal impedance is calculated in accordance with JESD 51.

This device contains a single 2-input NOR gate that performs the Boolean function Y = A• B or Y = A + B in positive logic.The SN74AHCT1G02 is characterized for operation from 40°C to 85°C.