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SN74ALS174

Application· Buffer/Storage Registers· Shift Registers· Pattern GeneratorsPinout SpecificationsSupply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 VInput voltage, VI . . . . . . . . . . . . . . . . . . . . . . ....

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SeekIC No. : 004498096 Detail

SN74ALS174: Application· Buffer/Storage Registers· Shift Registers· Pattern GeneratorsPinout SpecificationsSupply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

SN74ALS174 Data Sheet

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Part Number:
SN74ALS174
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Application

· Buffer/Storage Registers
· Shift Registers
· Pattern Generators


Pinout

Connection Diagram   Connection Diagram


Specifications

Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
Package thermal impedance, JA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
                                                                        N package . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
                                                                        NS package . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . 65°C to 150°C


Description

These 'ALS175 and 'AS175B  positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR) input. The 'ALS175 and 'AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These 'ALS175 and 'AS175B  circuits are fully compatible for use with most TTL circuits.




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