SN74ALVC162268

Supply voltage range, V_CC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .0.5 V to 4.6 V
Input voltage range, V_I: Except I/O ports (see Note 1) . . . . . . . . . . . ..0.5 V to V_CC + 0.5 V 
                                       I/O ports (see Notes 1 and 2) .. . . . . . . . . . . .0.5 V to V_CC + 0.5 V
Output-voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . .0.5 V to V_CC + 0.5 V
Output clamp current, I_OK (V_O < 0 or V_O > V_CC)  . . . . . . . . . . . . . . .. . . . . . . . .  . . . .±50 mA
Continuous output current, I_O (V_O = 0 to V_CC)  . . . . . . . . . . . . . . . .  . . . . . .. . . . . . .±50 mA
Continuous current through V_CC or GND  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .±100 mA
Maximum power dissipation at T_A = 55°C (in still air) (see Note 3): DGG package  . . . . . .1 W
                                                                                                         DL package . . .  . . .1.4 W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C 

The SN74ALVC162268 is a 12-bit to 24-bit registered bus exchanger, which is intended for use in applications where data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus. SN74ALVC162268 is designed specifically for low-voltage (3.3-V) V_CC operation; it is tested at 2.5-V, 2.7-V, and 3.3-V V_CC.

The SN74ALVC162268 provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs.

For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). These control terminals are registered so bus direction changes are synchronous with CLK.The B outputs, which are designed to sink up to 12 mA, include 26- resistors to reduce overshoot and undershoot.Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVC162268 is characterized for operation from 40°C to 85°C.