SN74ALVC16721

Features: Member of the Texas Instruments WidebusTM Family EPICTM (Enhanced-Performance Implanted CMOS) Submicron ProcessESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17B...

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SeekIC No. : 004498236 Detail

SN74ALVC16721: Features: Member of the Texas Instruments WidebusTM Family EPICTM (Enhanced-Performance Implanted CMOS) Submicron ProcessESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Us...

floor Price/Ceiling Price

Part Number:
SN74ALVC16721
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Features:

 Member of the Texas Instruments WidebusTM Family
EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
 ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
 Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
 Bus Hold On Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
 Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages



Pinout

  Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . .. . . .  . . . . .. . . . . . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . .  . . .0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .±50 mA
Continuous current through VCC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ±100mA
Maximum power package dissipation at TA = 55°C (in still air)(see Note 3):DGG package  . .  . . 1 W
                                                                                                                     DL package . .. . . . 1.4 W

Storage temperature range ,Tstg . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .  . .65°C to 150°C 
 


Description

This  SN74ALVC16721 20-bit flip-flop is designed specifically for low-voltage (3.3-V) VCC operation; it is tested at 2.5-V, 2.7-V, and 3.3-V VCC.

The SN74ALVC16721's 20 flip-flops are edgetriggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored.A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.

The SN74ALVC16721 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN74ALVC16721 is characterized for operation from 40°C to 85°C.




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