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SN74ALVCF162835

Features: · Member of the Texas Instruments Widebus™ Family· Ideal for Use in PC133 Register DIMM· Typical Output Skew . . . <250 ps· VCC = 3.3 V ± 0.3 V . . . Normal Range· VCC = 2.7 V to 3.6 V . . . Extended Range· VCC = 2.5 V ± 0.2 V· Rail-to-Rail Output Swing for Increased Noise Margi...

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SeekIC No. : 004498256 Detail

SN74ALVCF162835: Features: · Member of the Texas Instruments Widebus™ Family· Ideal for Use in PC133 Register DIMM· Typical Output Skew . . . <250 ps· VCC = 3.3 V ± 0.3 V . . . Normal Range· VCC = 2.7 V to ...

SN74ALVCF162835 Data Sheet

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Part Number:
SN74ALVCF162835
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

· Member of the Texas Instruments Widebus™ Family
· Ideal for Use in PC133 Register DIMM
· Typical Output Skew . . . <250 ps
· VCC = 3.3 V ± 0.3 V . . . Normal Range
· VCC = 2.7 V to 3.6 V . . . Extended Range
· VCC = 2.5 V ± 0.2 V
· Rail-to-Rail Output Swing for Increased Noise Margin
· Balanced Output Drivers . . . ±18 mA
· Low Switching Noise
· Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
· ESD Protection Exceeds JESD 22
  - 2000-V Human-Body Model (A114-A)
  - 200-V Machine Model (A115-A)
  - 1000-V Charged-Device Model (C101)


Pinout

Connection Diagram


Specifications
MIN
MAX
UNIT
VCC Supply voltage range
0.5
6.5
V
VI Input voltage range(2)
0.5
6.5
V
VO Output voltage range(2) (3)
0.5
VCC + 0.5
V
IIK Input clamp current
VI < 0 or VI < VCC
50
mA
IOK Output clamp current
VO < 0
50
mA
IO Continuous output current
±50
mA
Continuous current through each VCC or GND
±100
mA
JA Package thermal impedance(4)
 DGG package
40
/W
DGV package
DL package
Tstg Storage temperature range
-65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.


Description

This  SN74ALVCF162835 18-bit universal bus driver is designed for 2.3-V to 3.6-V VCC operation.

Data of SN74ALVCF162835 flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state.

The SN74ALVCF162835 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the SN74ALVC162835 (±12 mA) and SN74ALVC16835 (±24 mA).




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