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SN74ALVCH162836

Features: Member of the Texas Instruments Widebus(TM) FamilyEPIC(TM) (Enhanced-Performance Implanted CMOS) Submicron ProcessOutput Port Has Equivalent 26-W Series Resistors, So No External Resistors Are RequiredDesigned to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM SpecificationESD ...

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SeekIC No. : 004498281 Detail

SN74ALVCH162836: Features: Member of the Texas Instruments Widebus(TM) FamilyEPIC(TM) (Enhanced-Performance Implanted CMOS) Submicron ProcessOutput Port Has Equivalent 26-W Series Resistors, So No External Resistors...

SN74ALVCH162836 Data Sheet

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Part Number:
SN74ALVCH162836
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Member of the Texas Instruments
   Widebus(TM) Family
EPIC(TM) (Enhanced-Performance Implanted
   CMOS) Submicron Process
Output Port Has Equivalent 26-W  Series
   Resistors, So No External Resistors Are
   Required
Designed to Comply With JEDEC 168-Pin
   and 200-Pin SDRAM Buffered DIMM
   Specification
ESD Protection Exceeds 2000 V Per
   MIL-STD-883, Method 3015; Exceeds 200 V
   Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
   JESD 17
Bus Hold on Data Inputs Eliminates the
   Need for External Pullup/Pulldown
   Resistors
Package Options Include Plastic Shrink
   Small-Outline (DL), Thin Shrink
   Small-Outline (DGG), and Thin Very
   Small-Outline (DGV) Packages


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC   . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . .. . 0.5 V to 4.6 V
Input voltage range, VI  (see Note 1)  . . . . . . . .. . . . . . . . . . . . . . . . . . . .  . . . . 0.5 V to 4.6 V
Output voltage range, VO  (see Notes 1 and 2)  . .. . . . . . . . . . . . . . . . . 0.5 V to VCC  + 0.5 V
Input clamp current, IIK   (VI  < 0)  . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .  50 mA
Output clamp current, IOK  (VO  < 0)  . . . . . . . . . . . ..... . . . . . . . . . . . . . . . . . . . . . . . .  50 mA
Continuous output current, IO   . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .  . . . . . . ±50 mA
Continuous current through each VCC  or GND  . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  ±100 mA

Package thermal impedance, 0JA (see Note 3): DGG package  . . . . .. . ....... .. . . .. ... . . 81°C/W
                                                                           DGV package . . . .. . . . . . . .. ........ .. . . 86°C/W
                                                                           DL package . . . . . . . ...... . . . . ....... . . . 74°C/W
Storage temperature range, Tstg   . . . . . . . . . . . . . .  . . . . ......................... . . . . -65  to 150



Description

This SN74ALVCH162836 20-bit universal bus driver is designed for 1.65-V to 3.6-V VCC  operation.

Data flow from A to Y is controlled by the output-enable (OE) input. The SN74ALVCH162836 device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state.

The output port of SN74ALVCH162836 includes equivalent 26-W  series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state of SN74ALVCH162836 during power up or power down, OE should be tied to VCC  through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVCH162836 is characterized for operation from 40°C to 85°C.




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