SN74ALVCHG162282

Features:

·Member of the Texas Instruments WidebusE Family
·EPICE (Enhanced-Performance Implanted CMOS) Sub-Micron Process
·A-Port Outputs Have Equivalent 50-W Series Resistors and B-Port Outputs Have ·Equivalent 20-W Series Resistors, So No External Resistors Are Required
·ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
·Latch-Up Performance Exceeds 250 mA Per JESD 17
·Bus-Hold On Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
·Packaged in Thin Very Small-Outline Package


Pinout




Specifications

Supply voltage range, V_CC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, V_I: Except I/O ports (see Note 1)  . . . . . .. . . . . . . . . .0.5 V to V_CC + 0.5 V
I/O ports (see Notes 1 and 2)  . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . .0.5 V to V_CC + 0.5 V
Output voltage range, V_O (see Notes 1 and 2)  . . . . .  . . . . . . . . . .. . . . . . .0.5 V to VCC + 0.5 V
Input clamp current, I_IK (V_I < 0)  . . . . . .  . . .. . . .. .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .50 mA
Output clamp current, I_OK (V_O < 0)  . . . . . . . . . . . . . .. .. . . . . . . . . . . . .. . . .  . . . . . . . . . .50 mA
Continuous output current, I_O  . . . . . . . . . . . .  . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . ±50 mA
Package thermal impedance, _JA (see Note 3)  . . . .  . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .106/W
Storage temperature range, T_stg  . . . . .  . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . 65 to 150
 


Description

The SN74ALVCHG162282 is an 18-bit to 36-bit registered bus exchanger. This device is intended for use in applications where data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. SN74ALVCHG162282 is designed specifically for low-voltage (3.3-V) VCC operation.

The SN74ALVCHG162282 device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input. For data transfer in the B-to-A direction, the select (SEL ) input selects 1B or 2B data for the A outputs.
For data transferSN74ALVCHG162282  in the A-to-B direction, a two-stage pipeline is provided in the 1B path, with a single storage register in the 2B path. Data flow is controlled by the active-low output-enable (OE) and direction-control (DIR) input. DIR is registered to synchronize the bus direction changes with the clock.