SN74ALVTH16373

Features:

 State-of-the-Art Advanced BiCMOS Technology (ABT) WidebusE Design for 2.5-V and 3.3-V Operation and Low
    Static Power Dissipation
    Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
 High Drive (24/24 mA at 2.5-V and 32/64 mA at 3.3-V VCC)
 Power Off Disables Outputs, Permitting Live Insertion
 High-Impedance State During Power Up and Power Down Prevents Driver Conflict
 Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
 Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
 Latch-Up Performance Exceeds 250 mA Per JESD 17
 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and
    Exceeds 1000 V Using Charged-Device  Model, Robotic Method
 Flow-Through Architecture Facilitates Printed Circuit Board Layout
 Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
 Package Options Include Plastic Shrink
    Small-Outline (DL), Thin Shrink
    Small-Outline (DGG), Thin Very
    Small-Outline (DGV) Packages, and 380-mil
    Fine-Pitch Ceramic Flat (WD) Package 


Pinout




Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... . . 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . ..... . . 0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . ..... . . . 0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) .. 0.5 V to 7 V
Output current in the low state, IO: SN54ALVTH16373 . . . . . . . . . . . . . . . . . . . . . 96 mA
                                                         SN74ALVTH16373 . . . . . . . . . . . . . . .. . . . . 48 mA
                                                             SN74ALVTH16373 . . . . . . . . . . . .  . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, qJA (see Note 2): DGG package . . . . . . . . . . . . . . . 89°C/W
                                                                          DGV package . . . . . . . . . . . .  . . . 93°C/W
                                                                          DL package . . . . . . . . . . .. . .  . . . 94°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 65°C to 150°C 


Description

The SN74ALVTH16373  devices are 16-bit transparent D-type latches with 3-state outputs designed for 2.5-V or 3.3-V V_CC operation, but with the capability to provide a T_TL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These SN74ALVTH16373 devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.