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SN74AS374

Features: · D-Type Flip-Flops in a Single Package With 3-State Bus Driving True Outputs· Full Parallel Access for Loading· Buffered Control Inputs· Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPsPinoutSpecif...

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SeekIC No. : 004498411 Detail

SN74AS374: Features: · D-Type Flip-Flops in a Single Package With 3-State Bus Driving True Outputs· Full Parallel Access for Loading· Buffered Control Inputs· Package Options Include Plastic Small-Outline ...

SN74AS374 Data Sheet

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Part Number:
SN74AS374
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· D-Type Flip-Flops in a Single Package With
  3-State Bus Driving True Outputs
· Full Parallel Access for Loading
· Buffered Control Inputs
· Package Options Include Plastic
  Small-Outline (DW) Packages, Ceramic
  Chip Carriers (FK), and Standard Plastic (N)
  and Ceramic (J) DIPs


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 5.5 V
Package thermal impedance, qJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.


Description

These SN74AS374 octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relativelylow-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the SN74AS374 positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A SN74AS374 buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In  the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

SN74AS374 OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.




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